Utilizing reliable packaging technology, we manufacture ultra-large packaging products with dimensions up to 240mm x 240mm.
Today's most advanced artificial intelligence (AI) systems rely on larger, more complex chips and chip components from multiple technology nodes and foundries, placing unprecedented demands on advanced packaging. At the 2026 IEEE Electron Device and Technology Conference (ECTC), two research teams from Intel's foundry business proposed complementary solutions to address this shift: one team outlined an architectural blueprint for the next-generation AI chip packaging, while the other team addressed key manufacturing bottlenecks that arise as packaging sizes increase. For customers building AI platforms, these advancements mean higher system computing density, better energy efficiency, and the ability to scale next-generation workloads without requiring a completely new system architecture.
The advanced design team in this article elaborates on how to design and manufacture a High-Level Fine-Feature (HLFF) package with dimensions up to 240 mm x 240 mm, integrating computing chip arrays, High-Bandwidth Memory (HBM), and I/O components onto a single platform. Simultaneously, the assembly technology development team has developed material and process innovations to ensure the reliability of larger-sized packages. These combined efforts have propelled the transition of the HLFF package from concept to manufacturable reality, providing support for artificial intelligence data centers, scientific supercomputing, and large-scale model training systems.
Vision: To build the largest chip packaging in the field of artificial intelligence
For decades, the enhancement of computing performance has primarily been attributed to the reduction in transistor size. As computing demands accelerate, more components need to be integrated into a single package. Therefore, by assembling multiple chips into a unified system and integrating more silicon wafers at the packaging level, the performance of process nodes can be continuously improved through miniaturization.
Our advanced design team has scaled this approach to unprecedented levels using HLFF packaging. These designs integrate arrays of compute chips with HBM and I/O components, connected via embedded multi-chip interconnect bridge-T (EMIB-T) technology. These embedded silicon bridges provide high-density interconnects, enabling data transfer rates of over 64 gigabits per second (Gb/s)¹ per lane. For system designers, this translates to higher compute density and lower latency compared to multi-package solutions.
The study explored two configuration schemes. Configuration Scheme A utilizes an EMIB-T bridge for all inter-chip communication, thereby maximizing bandwidth and yield. Configuration Scheme B communicates with the processor through the substrate, reducing hardware complexity but sacrificing some performance. Both schemes offer different trade-offs between performance, cost, and design flexibility.
Both methods can be scaled up to 240mm x 240mm packaging, and their roadmaps not only encompass 12-fold mask integration but also extend further, approaching a 50-fold panel-level system.¹ Together, they define the path to building the largest and most complex AI computing platform to date.
Figure 1: The schematic diagram depicts the gradual reduction of package size from 8 times the mask size within a standard 120mm x 120mm package to a 240mm x 240mm High-Level Fine-Feature (HLFF) package.
Engineering challenge: What is required for scaling up
Transitioning from today's packaging scale to the HLFF scale involves simultaneously addressing several interrelated engineering issues.
The data transmission speed must be sufficiently fast. Within the package, the use of EMIB-T bridging technology with metal layer thickness less than 2 micrometers (µm) enables the inter-chip and chip-to-memory connection speeds required for AI workloads, achieving 64 Gb/s per channel. For communication outside the package, the study evaluated co-packaged copper cable connectors and co-packaged optical devices, concluding that they are the primary solutions for achieving the industry's expected next-generation external package speed target of 448 Gb/s.¹
Efficient power supply. At the HLFF size, the efficiency of power supply from the edge of the package becomes increasingly lower. This study proposes embedding silicon capacitors inside the substrate, directly beneath the chip, thereby providing up to 1 millifarad (mF) of local energy storage on each complete photomask chip area.¹ By moving the voltage regulator to the package or inside the package, it can also respond more quickly to the constantly changing power demands of the chip.
To enhance yield, the team proposed establishing a redundancy mechanism by adding backup channels to the existing communication channels. By merely adding three to four backup channels to each group of 64 channels, the bundled yield can be increased from approximately 97% to over 99%¹. At the scale of HLFF, this difference is crucial for achieving cost-effective and efficient production.
Maintain the package flatness. The research team simulated a situation where the package freely warps up to 7 millimeters at room temperature, which is sufficient to damage electrical connections and thermal contacts. The proposed solution combines a thick reinforcement ring, a low-expansion glass core substrate, and a multi-ball soldering process. During operation, applying a force of approximately 4500 newtons (N) or more to press down on the cooling hardware helps maintain the package nearly flat.
Kilowatt-level heat dissipation management. The total power of the HLFF package is expected to be 15 to 25 kilowatts (kW), and local hot spots require strong cooling. This study proposes a modular, cell-based cooling architecture that replaces traditional large cold plates. The architecture features independently controlled thermal zones and embedded sensors, aiming to achieve a cooling capacity of over 5 kW per module.
One challenge that the design scheme points out but does not fully address is packaging: sealing the chip onto the package with protective materials. As the package size increases, this process becomes increasingly difficult. This is precisely the focus of the assembly technology development team's work.
Packaging challenge: The difficulty of sealing increases in large-scale production.
Chip packaging relies on underfill materials, which flow into the space beneath the chip through capillary action, protecting the connection between the chip and the substrate. This method works well in small-sized packaging. However, as the package size and chip size increase, the distance that the underfill material needs to flow becomes longer, making it more difficult to achieve complete filling.
The impact of size scaling is evident: the maximum flow distance of underfill required for early packages was approximately 22 millimeters. Today's large EMIB packages have a flow distance exceeding 43 millimeters. With the 5- to 10-fold increase in mask size pursued by the HLFF architecture, the flow distance further increases, and the flow challenges become more complex. Differences in chip surface materials and variations in solder joint spacing increase resistance, making uniform flow more difficult to achieve. Eliminating air pockets or voids can reduce failure points and improve product reliability over its lifespan.
Figure 2: Demonstration of the flow distance of underfill in three generations of packaging designs: (a) 22.5 mm, (b) 28.5 mm, (c) 43.8 mm.
Large-scale gap-free process
Our assembly technology development team addresses packaging issues through three coordinated levers: materials, dispensing strategies, and curing.
Firstly, researchers optimized the underfill material to balance fluidity and reliability. Lower viscosity can extend the flow distance, but reducing the filler content increases thermal stress. The research team developed a direct flow testing method for typical packaging vehicles to determine a formulation that can extend the flow distance without sacrificing mechanical integrity.
Secondly, they redesigned the dispensing strategy. Instead of solely relying on edge dispensing, the team introduced multi-point dispensing technology, including dispensing between chips, to reduce the effective flow distance and improve coverage.
Finally, by optimizing the curing process, defects after dispensing were eliminated. The optimized curing conditions eliminated voids, resulting in a final package with a defect size of 3.4 millimeters that was completely void-free. These advancements collectively reduced the risk of defects and improved process consistency in large-scale production.
Figure 3: Comparison of the same encapsulation under two curing conditions. Figure (a) shows voids with a maximum diameter of 3.4 mm. Figure (b) shows the result obtained after using optimized curing conditions, with completely void-free results.
From concept to manufacturable reality
These innovations have been validated in various package types compliant with the HLFF architecture. The EMIB-based package, with a mask size exceeding 5 times that of the original, incorporates 18 chips (including 12 HBM stacks) and achieves a seamless package with a flow distance exceeding 40 millimeters. Larger-sized tiled EMIB packages, with dimensions exceeding 7 times the mask size, also demonstrate the effect of seamless packaging. In the Foveros 3D package, seamless packaging has been achieved with mask sizes of 2 times and 4 times that of the original. The 2-times mask design has passed comprehensive reliability tests, including 700 temperature cycles and over 1000 hours of high-temperature stress testing.
Although expanding to the full HLFF size remains a future step, this work establishes key process capabilities by linking architectural visions with manufacturable building blocks.
Next: Collaborate to solve the next scale problem
The research achievements presented at ECTC 2026 have advanced packaging technology to 7 times the mask size and defined an architecture with a maximum size of 240 mm x 240 mm. However, both teams are actively pushing for further advancements. Their roadmap aims to achieve packaging beyond 12 times the mask size in the near future, and ultimately realize a panel-level system approaching 50 times the mask size through continuous spacing reduction, integration of active bridge circuits, and co-packaging of optical components. Research on packaging technology is also progressing towards the same scale, aligning manufacturing capabilities with architectural goals.
These developments provide customers with a clear path to scale future AI systems with higher computing density, new interconnect technologies, and next-generation deployment models.
*Declaration: This article is created by the original author. The content of the article reflects his personal views. Our reprint is solely for sharing and discussion purposes and does not represent our endorsement or agreement. If there are any objections, please contact the back-end team.